EDJ1116DJBG - 1G bits DDR3 SDRAM

This page provides the datasheet information for the EDJ1116DJBG, a member of the EDJ1108DJBG 1G bits DDR3 SDRAM family.

Datasheet Summary

Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

Elpida Memory

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Datasheet Details

Part number	EDJ1116DJBG
Manufacturer	Elpida Memory
File Size	321.34 KB
Description	1G bits DDR3 SDRAM
Datasheet	EDJ1116DJBG Datasheet
Additional preview pages of the EDJ1116DJBG datasheet.

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Other Datasheets by Elpida Memory

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EDJ4216EFBG - 256M words x 16 bits 4G bits DDR3L SDRAM

Full PDF Text Transcription

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COVER DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG (128M words × 8 bits) EDJ1116DJBG (64M words × 16 bits) Specifications • Density: 1G bits • Organization — 16M words × 8 bits × 8 banks (EDJ1108DJBG) — 8M words × 16 bits × 8 banks (EDJ1116DJBG) • Package — 78-ball FBGA (EDJ1108DJBG) — 96-ball FBGA (EDJ1116DJBG) — Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD = 1.5V ± 0.

Published: Oct 13, 2014 |