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EDS1232CABB - 128M bits SDRAM

General Description

The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks.

All inputs and outputs are synchronized with the positive edge of the clock.

They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II).

Key Features

  • 2.5V power supply Clock frequency: 133MHz (max. ) Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently.
  • Burst read/write operation and burst read/single write operation capability.
  • Programmable burst length (BL): 1, 2, 4, 8 and full page.
  • 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8)  Interleave (BL = 1, 2, 4, 8).
  • Programmable /CAS latency (CL): 2, 3.

📥 Download Datasheet

Datasheet Details

Part number EDS1232CABB
Manufacturer Elpida Memory
File Size 564.84 KB
Description 128M bits SDRAM
Datasheet download datasheet EDS1232CABB Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY DATA SHEET 128M bits SDRAM EDS1232CABB, EDS1232CATA (4M words × 32 bits) Description The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II). Features • • • • • 2.5V power supply Clock frequency: 133MHz (max.