EDS2508APSA Description
The EDS2508AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDS2516AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input.
EDS2508APSA Key Features
- 3.3V power supply Clock frequency: 133MHz (max.) LVTTL interface Single pulsed /RAS 4 banks can operate simultaneously a
- Burst read/write operation and burst read/single write operation capability
- Programmable burst length (BL): 1, 2, 4, 8, full page
- Programmable /CAS latency (CL): 2, 3
- Byte control by DQM : DQM (EDS2508AP) : UDQM, LDQM (EDS2516AP)
- Refresh cycles: 8192 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh
- 1 Features