HB54R1G9F2 Overview
Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
HB54R1G9F2 Key Features
- 184-pin socket type package (dual lead out) Outline: 133.35mm (Length) × 43.18mm (Height) × 4.80mm (Thickness) Lead
- 2.5V power supply (VCC/VCCQ)
- SSTL-2 interface for all inputs and outputs
- Clock frequency: 143MHz/133MHz/125MHz (max.)
- Data inputs and outputs are synchronized with DQS
- 4 banks can operate simultaneously and independently (ponent)
- Burst read/write operation
- Programmable burst length: 2, 4, 8 Burst read stop capability
- Programmable burst sequence Sequential Interleave
- Start addressing capability Even and Odd