HM5225805B-B6 Overview
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank.
HM5225805B-B6 Key Features
- Programmable CAS latency: 2/3
- Byte control by DQM : DQM (HM5225805B/HM5225405B) : DQMU/DQML (HM5225165B)
- Refresh cycles: 8192 refresh cycles/64 ms
- 2 variations of refresh Auto refresh Self refresh