EDW2032BBBG Datasheet | Elpida

Features - Density: 2G bits - Organization - 4Mbit x 32 I/O x 16 banks - 8Mbit x 16 I/O x 16 banks - Package - 170-ball FBGA - Lead-free (Ro HS pliant) and Halogen-free - Power supply: - VDD: 1.6V/1.5V ± 3% and 1.35V ± 3% - VDDQ: 1.6V/1.5V ± 3% and 1.35V ± 3% - Data rate: 7.0Gbps/6.0Gbps/5.0Gbps (max.) - 16 internal banks - Four bank groups for t CCDL = 3t CK - 8n prefetch architecture: 256 bit per array Read or Write access for x32; 128 bit for x16 - Burst length (BL): 8 only - Programmable CAS latency: 6 to 20 - Programmable Write latency: 3 to 7 - Programmable CRC READ latency: 1 to 3 - Programmable CRC WRITE latency: 8 to 14 - Programmable EDC hold pattern for CDR - Precharge: auto precharge option for each burst access - Refresh: auto-refresh, self-refresh - Refresh cycles: 16384 cycles/32ms - Interface: Pseudo open drain (POD-15) - On-die termination (ODT): nom. values of 60Ω or 120Ω - Pseudo open drain (POD-15) patible outputs - 40Ω pulldown - 60Ω pullup - ODT and output driver strength auto-calibration with external resistor ZQ pin (120Ω) - Programmable termination and driver strength offsets - Selectable external or internal VREF for data inputs; programmable offsets for internal VREF - Separate external VREF for address / mand inputs - Operating case temperature range - TC = 0°C to +95°C - x32/x16 mode configuration set at power-up with EDC pin - Single ended interface for data, address and mand - Quarter data-rate differential clock inputs CK, /CK for address and mands - Two half data-rate differential clock inputs WCK, /WCK, each associated with two data bytes (DQ, /DBI,...