EM47EM1688MBB Overview
Key Features
- JEDEC Standard VDD/VDDQ = 1.35V-0.065/+0.1V
- Backward compatible to VDD/ VDDQ = 1.5V ±0.075V
- All inputs and outputs are compatible with SSTL_15 interface
- Fully differential clock inputs (CK, /CK) operation
- Posted CAS by programmable additive latency
