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EM47EM3288MBA
8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM
Features
• VDD/VDDQ = 1.35V -0.065/+0.1V. • Backward compatible to VDD = VDDQ = 1.5V
±0.075V.Supports DDR3L devices to be backward compatible in 1.5V applications. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS by programmable additive latency • Bust length: 4 with Burst Chop (BC) and 8. • CAS Write Latency (CWL): 5,6,7,8 • CAS Latency (CL): 5,6,7,8,9,10 • Write Latency (WL) =Read Latency (RL) -1. • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition
with CK transition. • DM mask write data-in at the both rising and falling
edges of the data strobe.
EM47EM3288MBA Datasheet
