Datasheet Summary
8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM
Features
- VDD/VDDQ = 1.35V -0.065/+0.1V.
- Backward patible to VDD = VDDQ = 1.5V
±0.075V.Supports DDR3L devices to be backward patible in 1.5V applications.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS by programmable additive latency
- Bust length: 4 with Burst Chop (BC) and 8.
- CAS Write Latency (CWL): 5,6,7,8
- CAS Latency (CL): 5,6,7,8,9,10
- Write Latency (WL) =Read Latency (RL) -1.
- Bi-directional Differential Data Strobe (DQS).
- Data inputs on DQS centers when write.
- Data outputs on DQS, /DQS edges when read.
- On chip DLL align DQ, DQS and /DQS transition with CK...