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EM47EM3288SBA - 8Gb (32M x 8Bank x 32) Double DATA RATE 3 Stack SDRAM

Description

Revision 0.3 (Apr.

2014) -Update tFAW.

Apr.

Features

  • JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
  • All inputs and outputs are compatible with SSTL_15 interface.
  • Fully differential clock inputs (CK, /CK) operation.
  • Eight Banks.
  • Posted CAS by programmable additive latency.
  • Bust length: 4 with Burst Chop (BC) and 8.
  • CAS Write Latency (CWL): 5,6,7,8.
  • CAS Latency (CL): 5,6,7,8,9,10.
  • Write Latency (WL) =Read Latency (RL) -1.
  • Bi-directional Differential Data Strobe (.

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Datasheet Details

Part number EM47EM3288SBA
Manufacturer Eorex
File Size 0.99 MB
Description 8Gb (32M x 8Bank x 32) Double DATA RATE 3 Stack SDRAM
Datasheet download datasheet EM47EM3288SBA Datasheet

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Full PDF Text Transcription

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Revision History Revision 0.1 (May. 2012) -First release. Revision 0.2 (Feb. 2013) -Update ZQ pins description. Revision 0.3 (Apr. 2014) -Update tFAW. EM47EM3288SBA Apr. 2014 1/39 www.eorex.com EM47EM3288SBA 8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM Features • JEDEC Standard VDD/VDDQ = 1.5V±0.075V. • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS by programmable additive latency • Bust length: 4 with Burst Chop (BC) and 8. • CAS Write Latency (CWL): 5,6,7,8 • CAS Latency (CL): 5,6,7,8,9,10 • Write Latency (WL) =Read Latency (RL) -1. • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read.
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