S1L50000 Datasheet | Epson

.. DATA SHEET ASIC S1L50000 S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V tolerant I/O buffers. - - - Ultra-high-speed, high density and low power consumption Low voltage operation: 3.3V and 2.0V Number of raw gates: 28,710 ~ 815,468 gates Œ Features - - - Process Integration Operating Speed 0.35µm 2/3/4 layer metalization CMOS process A maximum of 815,468 gates (2 input NAND gate equivalent) Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ) (2-input pair NAND, F/O = 2, Typical wire load) Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used. 400 ps (3.3V Typ), 1.30 ns (2.0V Typ) (F/O = 2, Typical wire load) Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used. 2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ) (CL = 15 p F) Input/Output TTL/CMOS/LVTTL patible TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI Built-in pull-up and pull-down resistors can be usable. (2 types for each resistor value) Normal, 3-state, bi-directional, PCI IOL = 0.1, 1, 3, 8, 12, 24 m A selectable (Built-in level shifter is used at 5.0V) IOL = 0.1, 1, 2, 6, 12 m A selectable (at 3.3V) IOL = 0.05, 0.3, 0.6, 2, 4 m A selectable (at 2.0V) Asynchronous 1-port, asynchronous 2-port Operation supported by using level-shifter circuit Internal logic: Operation supported by low voltage I/O Buffer: Built-in interfaces of both high and low voltages possible - - I/F Levels Input Modes - - Output Modes Output Drive - - RAM Dual Power - Operation possible at VDD = 2.0 ± 0.2V EPSON ELECTRONICS AMERICA, INC. i150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238 DATA SHEET ASIC S1L50000 Œ LINE UP The S1L50000 Series prises 11 types of masters, from which the customer is able to select the master most suitable. Total...