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EM636165-XXI - 1Mega x 16 Synchronous DRAM

General Description

Table 1.

Pin Details of EM636165 Description Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Key Features

  • Fast access time: 5/5.5/6.5/7.5 ns Fast clock rate: 166/143/125/100 MHz Self refresh mode: standard and low power Internal pipelined architecture 512K word x 16-bit x 2-bank Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function Individual byte controlled by LDQM and UDQM Auto Refresh and Self Refresh 4096 refresh cycles/64ms CKE pow.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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EtronTech Features • • • • • • Fast access time: 5/5.5/6.5/7.5 ns Fast clock rate: 166/143/125/100 MHz Self refresh mode: standard and low power Internal pipelined architecture 512K word x 16-bit x 2-bank Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function Individual byte controlled by LDQM and UDQM Auto Refresh and Self Refresh 4096 refresh cycles/64ms CKE power down mode Single +3.3V±0.3V power supply Interface: LVTTL 50-pin 400 mil plastic TSOP II package Lead Free Package available EM636165-XXI Preliminary (Rev. 1.