Datasheet4U Logo Datasheet4U.com

EM639165 - 8M x 16 bit Synchronous DRAM

Description

Table 3.

Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Features

  • Fast access time from clock: 4.5/5/5.4 ns.
  • Fast clock rate: 200/166/143 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • 2M word x 16-bit x 4-bank.
  • Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function.
  • Auto Refresh and Self Refresh.
  • 4096 refresh cycles/64ms.
  • CKE power down mode.
  • Single +3.3V ±0.3V power supply.
  • Operating tem.

📥 Download Datasheet

Datasheet preview – EM639165

Datasheet Details

Part number EM639165
Manufacturer Etron Technology
File Size 810.27 KB
Description 8M x 16 bit Synchronous DRAM
Datasheet download datasheet EM639165 Datasheet
Additional preview pages of the EM639165 datasheet.
Other Datasheets by Etron Technology

Full PDF Text Transcription

Click to expand full text
EtronTech EM639165 8M x 16 bit Synchronous DRAM (SDRAM) Advance (Rev. 3.1, Jun. /2024) Features  Fast access time from clock: 4.5/5/5.4 ns  Fast clock rate: 200/166/143 MHz  Fully synchronous operation  Internal pipelined architecture  2M word x 16-bit x 4-bank  Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Single +3.3V ±0.3V power supply  Operating temperature: TA = 0 ~ 70°C (Commercial)  Interface: LVTTL  Package: Pb free and Halogen free - 54-pin 400 mil plastic TSOP II - 54-ball 8.0 x 8.0 x 1.
Published: |