EM6GE16EWXC Datasheet | EtronTech

Etron Tech Etron Confidential Features - JEDEC Standard pliant - Power supplies: VDD & VDDQ = +1.5V ± 0.075V - Operating temperature: 0~95°C (TC) - Supports JEDEC clock jitter specification - Fully synchronous operation - Fast clock rate: 667/800/933MHz - Differential Clock, CK & CK# - Bidirectional differential data strobe -DQS & DQS# - 8 internal banks for concurrent operation - 8n-bit prefetch architecture - Internal pipeline architecture - Precharge & active power down - Programmable Mode & Extended Mode registers - Additive Latency (AL): 0, CL-1, CL-2 - Programmable Burst lengths: 4, 8 - Burst type: Sequential / Interleave - Output Driver Impedance Control - 8192 refresh cycles / 64ms - Average refresh period 7.8µs @ 0 TC +85 3.9µs @ +85 TC +95 - Write Leveling - OCD Calibration - Dynamic ODT (Rtt_Nom & Rtt_WR) - Ro HS pliant - Auto Refresh and Self Refresh - 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Advanced (Rev. 1.2, Dec. /2013) Overview The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to ply with all key DDR3 DRAM key Features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA...