EM6GE16EWXC Datasheet PDF (256M x 16 bit DDR3 Synchronous DRAM)

EM6GE16EWXC - 256M x 16 bit DDR3 Synchronous DRAM

Description

Table 3.

Differential Clock: CK and CK# are driven by the system clock.

All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#.

Features

JEDEC Standard Compliant.
Power supplies: VDD & VDDQ = +1.5V ± 0.075V.
Operating temperature: 0~95°C (TC).
Supports JEDEC clock jitter specification.
Fully synchronous operation.
Fast clock rate: 667/800/933MHz.
Differential Clock, CK & CK#.
Bidirectional differential data strobe -DQS & DQS#.
8 internal banks for concurrent operation.
8n-bit prefetch architecture.
Internal pipeline architecture.

Datasheet Details

Part number	EM6GE16EWXC
Manufacturer	EtronTech
File Size	815.66 KB
Description	256M x 16 bit DDR3 Synchronous DRAM
Datasheet	EM6GE16EWXC Datasheet
Additional preview pages of the EM6GE16EWXC datasheet.

📁 Similar Datasheet

EM6GE16EWAKG - 256M x 16 bit DDR3 Synchronous DRAM (Etron Technology)

EM6GB08EWUA - 64M x 8 bit DDR3 Synchronous DRAM (Etron Technology)

EM6GC16EWBH - 64M x 16 bit DDR3 Synchronous DRAM (Etron Technology)

EM6GC16EWKE - 64M x 16 bit DDR3 Synchronous DRAM (Etron Technology)

EM6GD16EWBH - 128M x 16 bit DDR3 Synchronous DRAM (Etron Technology)

EM60000 - Stereo Four Channels 8-Bit Based Sound Processor (ELAN Microelectronics Corp)

EM60001 - Stereo Four Channels 8-Bit Based Sound Processor (ELAN Microelectronics)

EM60101 - Stereo Four Channels 8-Bit Based Sound Processor (ELAN Microelectronics)

EM6011 - Electret Condenser Microphone (UNIS)

EM60201 - Stereo Four Channels 8-Bit Based Sound Processor (ELAN Microelectronics)

Full PDF Text Transcription

Click to expand full text

EtronTech Etron Confidential Features • JEDEC Standard Compliant • Power supplies: VDD & VDDQ = +1.5V ± 0.075V • Operating temperature: 0~95°C (TC) • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate: 667/800/933MHz • Differential Clock, CK & CK# • Bidirectional differential data strobe -DQS & DQS# • 8 internal banks for concurrent operation • 8n-bit prefetch architecture • Internal pipeline architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Additive Latency (AL): 0, CL-1, CL-2 • Programmable Burst lengths: 4, 8 • Burst type: Sequential / Interleave • Output Driver Impedance Control • 8192 refresh cycles / 64ms - Average refresh period 7.8µs @ 0 TC +85 3.

Published: Jun 26, 2014 |