XRK79892 Datasheet | Exar

.. xr JANAUARY 2005 PRELIMINARY REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. Features GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide...