XRK799J93 Overview
The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.
XRK799J93 Key Features
- Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead TQF
- (510) 668-7000
- FAX (510) 668-7017
- Differential PLL clock reference (CLK0 pulldown, CLK0 pulldown) Clock 1
- Differential PLL clock reference (CLK1 pulldown, CLK1 pulldown) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB
- if CLK0 is selected 1