XRT91L31 Datasheet | Exar

DESCRIPTION The XRT91L31 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase Locked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the ining serial data stream. The internal CDR unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. Either the internally recovered clock or the externally recovered clock can be used for loop timing applications. The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system interface in both receive and transmit directions. The transmit section includes an option to accept a FIGURE 1. BLOCK DIAGRAM OF XRT91L31 parallel clock signal from the framer/mapper to synchronize the transmit section timing. The device can internally monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability recover SONET/SDH framing and to byte align the receive serial data stream into the 8-bit parallel bus. APPLICATIONS - SONET/SDH-based Transmission Systems - Add/Drop Multiplexers - Cross Connect Equipment - ATM and Multi-Service Switches, Routers and Switch/Routers - DSLAMS - SONET/SDH Test Equipment - DWDM Termination Equipment STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER TXDI[7:0] TXPCLK_IO REFCLKP/N TTLREFCLK PISO (Parallel Input Serial Output) Re-Timer TXOP/N MUX Div by 8 CMU DLOOP RLOOPS ALOOP CDRAUXREFCLK RXDO[7:0] SIPO (Serial Input Parallel Output) CDR MUX RXIP/N XRXCLKIP/N RXPCLKO Div by 8 Loop Filters Control Block Clock Control CAP1N CAP2N...