XRT91L34 Datasheet | Exar

DESCRIPTION The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the ining serial data stream. The device internally monitors Loss of Lock (LOL) conditions and automatically mutes recovered data upon Loss of Signal (LOS) conditions. CLOCK AND DATA RECOVERY OVERVIEW The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the LVDS or Differential LVPECL receiver and generates a clock that is the same frequency as the ining data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. All four channels share a single 77.76MHz or 19.44MHz reference clock. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL FIGURE 1. BLOCK DIAGRAM OF XRT91L34 attempts to lock onto the ining receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/ mapper device. When the SDEXT is de-asserted by the optical module or when internal DLOS is asserted, the receive serial data output will be forced to a logic zero state for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid ining data. When the SDEXT bees active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery...