DESCRIPTION
Eight ouputs, arranged in four banks, can each drive 75Ω terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. Banks A, B, C (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated three-level inputs. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to +12 time units can be created. The XRK4993’s divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, FIGURE 1. BLOCK DIAGRAM OF THE XRK4993 all the outputs except synchronously disabled.
Exar Corporation
