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Dual P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
‐30V
RDSON (MAX.)
50mΩ
ID
‐5A
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
VGS ID IDM PD Tj, Tstg
EMB50B03G
LIMITS ±20 ‐5 ‐4 ‐20 2 0.8
‐55 to 150
UNIT V
A
W °C
THERMAL RESISTANCE RATINGS THERMAL RESISTANCE
SYMBOL
Junction‐to‐Case
RJC
Junction‐to‐Ambient3
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1％ 362.5°C / W when mounted on a 1 in2 pad of 2 oz copper.
TYPICAL
MAXIMUM 25 62.
EMB50B03G Datasheet
