EMD07P03A Datasheet | Excelliance MOS

P‐Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS ‐30V RDSON (MAX.) 8mΩ ‐70A UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Gate‐Source Voltage Continuous Drain Current Pulsed Drain Current1 TC = 25 °C TC = 100 °C Avalanche Current Avalanche Energy L = 0.1m H, ID=‐50A, RG=25Ω Power Dissipation TC = 25 °C TC = 100 °C Operating Junction & Storage Temperature Range VGS ID IDM IAS EAS PD Tj, Tstg ±25 ‐70 ‐50 ‐150 ‐50 125 62.5 25 ‐55 to 150 100% UIS testing in condition of VD=‐15V, L=0.1m H, VG=‐10V, IL=‐40A, Rated VDS=‐30V P‐CH THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction‐to‐Case RJC Junction‐to‐Ambient3 RJA 1Pulse width limited by maximum junction temperature. 2Duty cycle ...