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EMF04P02H
P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
D
BVDSS
‐20V
RDSON (MAX.)
5.5mΩ
ID
‐72A
G
UIS, Rg 100% Tested
S
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
Gate‐Source Voltage
VGS
±12
Continuous Drain Current Pulsed Drain Current1
TC = 25 °C
‐72
ID
TC = 100 °C
‐45
IDM
‐240
Avalanche Current
IAS
‐48
Avalanche Energy
L = 0.1mH, IAS=‐48A, RG=25Ω
EAS
115
Repetitive Avalanche Energy2
L = 0.05mH
EAR
57
Power Dissipation
TC = 25 °C TC = 100 °C
Operating Junction & Storage Temperature Range
PD Tj, Tstg
50 20 ‐55 to 150
100% UIS testing in condition of VD=‐15V, L=0.