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N & P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH
P‐CH
BVDSS
30V
‐30V
RDSON (MAX.)
21mΩ 35mΩ
ID
7.5A
‐6A
UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free ESD Protection
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Avalanche Current
Avalanche Energy
L = 0.1mH, ID=7.5A, RG=25Ω(N) L = 0.1mH, ID=‐6A, RG=25Ω(P)
Repetitive Avalanche Energy2
L = 0.05mH
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
ID
IDM IAS EAS
EAR PD Tj, Tstg
EMZB21C03G
LIMITS
N‐CH
P‐CH
±20
±20
7.5
‐6
5.5
‐5
30
‐24
7.5
‐6
2.8
1.8
UNIT V
A
mJ
1.4
0.