74ABT16500 Datasheet | Fairchild Semiconductor

74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs April 1993 Revised January 1999 74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs General Description The ABT16500 18-bit universal bus transceiver bines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in...