74ACTQ74 Datasheet PDF - Fairchild Semiconductor Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop Specs

74ACTQ74 - Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

Datasheet Summary

Description

The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the positive edge of the clock pulse.

Features

GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s 4 kV m.

Datasheet Details

Part number	74ACTQ74
Manufacturer	Fairchild Semiconductor
File Size	215.29 KB
Description	Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
Datasheet	74ACTQ74 Datasheet
Additional preview pages of the 74ACTQ74 datasheet.

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Full PDF Text Transcription

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74ACTQ74 Quiet Series Dual D-Type March 1993 Revised November 1999 74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Published: Apr 3, 2005 |