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74LCX112 - Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop

General Description

The LCX112 is a dual J-K flip-flop.

Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs.

These devices are edge sensitive and change state on the negative going transition of the clock pulse.

Key Features

  • s 5V tolerant inputs s 2.3V.
  • 3.6V VCC specifications provided s 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s ±24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 2000V Ordering Code: Order Number Package Number Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs June 1998 Revised February 2001 74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input. LCX devices are designed for low voltage (3.3V or 2.5) operation with the added capability of interfacing to a 5V signal environment.