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74LCX126 - Low Voltage Quad Buffer

General Description

The LCX126 contains four independent non-inverting buffers with 3-STATE outputs.

Each output is disabled when the associated output-enable (OE) input is LOW.

The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

Key Features

  • s 5V tolerant inputs and outputs s 2.3V.
  • 3.6V VCC specifications provided s 5.5 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s ±24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 100V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to GN.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LCX126 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs September 2000 Revised July 2003 74LCX126 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs General Description The LCX126 contains four independent non-inverting buffers with 3-STATE outputs. Each output is disabled when the associated output-enable (OE) input is LOW. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX126 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 5.5 ns tPD max (VCC = 3.