Datasheet4U Logo Datasheet4U.com

74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Download the 74LS112A datasheet PDF. This datasheet also covers the 74LS112 variant, as both devices belong to the same dual negative-edge-triggered master-slave j-k flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is processed by the flip-flop on the falling edge of the clock pulse.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LS112_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Motorola
74LS112 Dual J-K Negative-edge-triggered Flip-Flops Hitachi Semiconductor
74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Motorola
74LS10 TRIPLE 3-INPUT NAND GATE ON Semiconductor
74LS107 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops ETC

Other Datasheets by Fairchild (now onsemi)

Part Number Description
74LS11 Triple 3-Input AND Gate
74LS10 Triple 3-Input NAND Gate
74LS12 Dual Retriggerable One-Shot
74LS12 Dual Retriggerable One-Shot
74LS123 Dual Retriggerable One-Shot

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated.