This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | 74LS112A |
|---|---|
| Datasheet | 74LS112A 74LS112 Datasheet (PDF) |
| File Size | 52.01 KB |
| Manufacturer | Fairchild (now onsemi) |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
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This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse.
| Brand Logo | Part Number | Description | Other Manufacturers |
|---|---|---|---|
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74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola |
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74LS112 | Dual J-K Negative-edge-triggered Flip-Flops | Hitachi Semiconductor |
See all Fairchild (now onsemi) datasheets
| Part Number | Description |
|---|---|
| 74LS11 | Triple 3-Input AND Gate |
| 74LS10 | Triple 3-Input NAND Gate |
| 74LS12 | Dual Retriggerable One-Shot |
| 74LS12 | Dual Retriggerable One-Shot |
| 74LS123 | Dual Retriggerable One-Shot |
| 74LS125 | Quad 3-STATE Buffer |
| 74LS126 | Quad 3-STATE Buffer |
| 74LS13 | Dual 4-Input Schmitt Trigger |
| 74LS132 | Quad 2-Input NAND Gate |
| 74LS136 | Quad 2-Input Exclusive-OR Gate |
