| Part number | 74LS112A |
|---|---|
| Datasheet | 74LS112A / 74LS112 Datasheet PDF (Download) |
| File Size | 52.01 KB |
| Manufacturer | Fairchild (now onsemi) |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
|
|
This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola |
 |
74LS112 | Dual J-K Negative-edge-triggered Flip-Flops | Hitachi Semiconductor |
