Datasheet Details
| Part number | 74LS112A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 52.01 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Datasheet | 74LS112A 74LS112 Datasheet (PDF) |
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Overview: DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with.
This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | 74LS112A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 52.01 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Datasheet | 74LS112A 74LS112 Datasheet (PDF) |
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This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flop on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse.
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| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
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74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola |
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74LS112 | Dual J-K Negative-edge-triggered Flip-Flops | Hitachi Semiconductor |
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