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74LS138 - Decoder/Demultiplexer

General Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can be used to minimize the effects of system decoding.

Key Features

  • s Designed specifically for high speed: Memory decoders Data transmission systems s DM74LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception s DM74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers s Schottky clamped for high performance s Typical propagation delay (3 levels of logic) DM74LS138 DM74LS139 DM74LS138 DM74LS139 21 ns 21 ns 32 mW 34 mW s Typical power dissipation Ordering Code: Order Number DM74LS138M DM74LS138SJ.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74LS138 • DM74LS139 Decoder/Demultiplexer August 1986 Revised March 2000 DM74LS138 • DM74LS139 Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs.