Datasheet4U Logo Datasheet4U.com

74LVQ373 - Low Voltage Octal Transparent Latch

Datasheet Summary

Description

The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications.

The latches appear transparent to the data when Latch Enable (LE) is HIGH.

When LE is low, the data satisfying the input timing requirements is latched.

Features

  • n Ideal for low power/low noise 3.3V.

📥 Download Datasheet

Datasheet preview – 74LVQ373

Datasheet Details

Part number 74LVQ373
Manufacturer Fairchild Semiconductor
File Size 102.06 KB
Description Low Voltage Octal Transparent Latch
Datasheet download datasheet 74LVQ373 Datasheet
Additional preview pages of the 74LVQ373 datasheet.

📁 Similar Datasheet

  • 74LVQ373 - OCTAL D-TYPE LATCH (STMicroelectronics)
  • 74LVQ32 - QUAD 2-INPUT OR GATE (STMicroelectronics)
  • 74LVQ00 - QUAD 2-INPUT NAND GATE (STMicroelectronics)
  • 74LVQ02 - QUAD 2-INPUT NOR GATE (STMicroelectronics)
  • 74LVQ04 - HEX INVERTER (STMicroelectronics)
  • 74LVQ08 - QUAD 2-INPUT AND GATE (STMicroelectronics)
  • 74LVQ125 - QUAD BUS BUFFERS 3-STATE (STMicroelectronics)
  • 74LVQ138 - 3 TO 8 LINE DECODER INVERTING (STMicroelectronics)
  • 74LVQ14 - HEX SCHMITT INVERTER (STMicroelectronics)
  • 74LVQ157 - LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER (STMicroelectronics)
Other Datasheets by Fairchild Semiconductor
  • 74LVQ374 - Low Voltage Octal D-Type Flip-Flop
  • 74LVQ32 - Low Voltage Quad 2-Input OR Gate
  • 74LVQ00 - Low Voltage Quad 2-Input NAND Gate
  • 74LVQ02 - Low Voltage Quad 2-Input NOR Gate
  • 74LVQ04 - Low Voltage Hex Inverter
  • 74LVQ08 - Low Voltage Quad 2-Input AND Gate
  • 74LVQ125 - Low Voltage Quad Buffer
  • 74LVQ138 - Low Voltage 1-of-8 Decoder/Demultiplexer

Full PDF Text Transcription

Click to expand full text
74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs May 1998 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features n Ideal for low power/low noise 3.
Published: |