DESCRIPTION
These 8 bit D-Type latchs are controlled by a latch enable input (LE) and an output enable PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 17, 18 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3 State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S OE H L L L LE X L H H D X X L H OUTPUTS Q Z NO CHANGE * L H X: Don’t care Z: High impedance * Q output are latched at the timewhen the LE input is taken low logic level. LOGIC DIAGRAM 2/10 74LVQ373 ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -6...
STMicroelectronics
