| Part number | 74S112 |
|---|---|
| Download | 74S112 Datasheet (PDF) |
| File Size | 42.41 KB |
| Manufacturer | Fairchild |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
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| Part Number | Description |
|---|---|
| 74S138 | Decoder/Demultiplexer |
| 74S139 | Decoder/Demultiplexer |
| 74S140 | Dual 4-Input NSND Line Driver |
| 74S153 | Dual 1-of-4 Line Data Selector/Multiplexer |
| 74S157 | Quad 1 of 2 Line Data Selectors/Multiplexers |
This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
