74VCX16244 Datasheet | Fairchild Semiconductor

Description The VCX16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The 74VCX16244 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.2V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s t PD 2.5 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) r24 m A @ 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 m A s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX16244G (Note 2)(Note 3) 74VCX16244MTD (Note 3) Package Number BGA54A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: Ordering Code “G” indicates Tray. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS012168 .fairchildsemi. Logic Symbol Pin Descriptions Pin Names OEn I0- I15 O0- O15 NC Description Output Enable Input (Active LOW) Inputs Outputs No Connect Connection Diagrams Pin Assignment for TSSOP FBGA Pin Assignments 1 A B C D...