74VCX32374 Datasheet | Fairchild Semiconductor

Description The VCX32374 contains thirty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are mon to each byte and can be shorted together for full 32-bit operation. The 74VCX32374 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O patibility up to 3.6V. The 74VCX32374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.2V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s t PD 3.0 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) ±24 m A @ 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 m A s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX32374G (Note 2)(Note 3) Package Number BGA96A Package Descriptions 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation DS500402 .fairchildsemi. Connection Diagram Pin Descriptions Pin Names OEn CPn I0- I31 O0- O31 Description Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs FBGA Pin Assignments 1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3...