74VCX32373 Datasheet | Fairchild Semiconductor

Description The VCX32373 contains thirty-two non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX32373 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O patibility up to 3.6V. The 74VCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V- 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s t PD (In to On) 3.0 ns max for 3.0V to 3.6V VCC 3.4 ns max for 2.3V to 2.7V VCC 6.8 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) ±24 m A @ 3.0V VCC ±18 m A @ 2.3V VCC ±6 m A @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 m A s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Ordering Number Package Number 74VCX32373GX (Note 2) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500567 .fairchildsemi. Preliminary 74VCX32373 Connection Diagram Pin Assignment for FBGA Pin Descriptions Pin Names OEn LEn I0- I31 O0- O31 Description Output Enable Input (Active LOW) Latch Enable Input Inputs...