74VHC573 Datasheet | Fairchild Semiconductor

74VHC573 Octal D-Type Latch with 3-STATE Outputs 74VHC573 Octal D-Type Latch with 3-STATE Outputs May 2007 tm Features - High Speed: t PD = 5.0ns (Typ.) at VCC = 5V - High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) - Power Down Protection is provided on all inputs - Low Noise: VOLP = 0.6V (Typ.) - Low Power Dissipation: ICC = 4µA (Max.) @ TA = 25°C - Pin and function patible with 74HC573 General Description The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC573M 74VHC573SJ 74VHC573MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names D0- D7 LE OE O0- O7 Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Outputs ©1993 Fairchild Semiconductor Corporation 74VHC573 Rev. 1.3 .fairchildsemi. 74VHC573 Octal D-Type Latch with 3-STATE Outputs Logic Symbol IEEE/IEC...