Datasheet4U Logo Datasheet4U.com

74VHC573 - Octal D-Type Latch

General Description

The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

Key Features

  • High Speed: tPD = 5.0ns (Typ. ) at VCC = 5V.
  • High Noise Immunity: VNIH = VNIL = 28% VCC (Min. ).
  • Power Down Protection is provided on all inputs.
  • Low Noise: VOLP = 0.6V (Typ. ).
  • Low Power Dissipation: ICC = 4µA (Max. ) @ TA = 25°C.
  • Pin and function compatible with 74HC573 General.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74VHC573 OCTAL D-TYPE LATCH STMicroelectronics
74VHC574 Octal D-Type Flip-Flop STMicroelectronics
74VHC540 Octal Bus Buffer Motorola
74VHC540 Octal Bus Buffer ON Semiconductor
74VHC541 OCTAL BUS BUFFER STMicroelectronics

Other Datasheets by Fairchild (now onsemi)

Part Number Description
74VHC574 Octal D-Type Flip-Flop
74VHC541 Octal Buffer/Line Driver
74VHC595 8-Bit Shift Register
74VHC00 Quad 2-Input NAND Gate
74VHC02 Quad 2-Input NOR Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74VHC573 Octal D-Type Latch with 3-STATE Outputs 74VHC573 Octal D-Type Latch with 3-STATE Outputs May 2007 tm Features ■ High Speed: tPD = 5.0ns (Typ.) at VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power Down Protection is provided on all inputs ■ Low Noise: VOLP = 0.6V (Typ.) ■ Low Power Dissipation: ICC = 4µA (Max.) @ TA = 25°C ■ Pin and function compatible with 74HC573 General Description The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an Output Enable input (OE).