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74VHC573 - OCTAL D-TYPE LATCH

General Description

The 74VHC573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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® 74VHC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (Max.) M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC573M 74VHC573T outputs will follow the data inputs precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.