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CD4027BCN - Dual J-K Master/Slave Flip-Flop

Download the CD4027BCN datasheet PDF. This datasheet also covers the CD4027BC variant, as both devices belong to the same dual j-k master/slave flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors.

Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs.

Key Features

  • s Wide supply voltage range: s High noise immunity: 3.0V to 15V 0.45 VDD (typ. ) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Low power: 50 nW (typ. ) s Medium speed operation: 12 MHz (typ. ) with 10V supply Ordering Code: Order Number CD4027BCM CD4027BCN Package Number M16A N16E Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD4027BC-FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CD4027BC Dual J-K Master/Slave Flip-Flop National Semiconductor
CD4027B CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP RCA
CD4027B CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP Texas Instruments
CD4027BE CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP Texas Instruments
CD4027BF CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP Texas Instruments

Other Datasheets by Fairchild (now onsemi)

Part Number Description
CD4027BC Dual J-K Master/Slave Flip-Flop
CD4027BCM Dual J-K Master/Slave Flip-Flop
CD4022BC Divide-by-8 Counter/Divider
CD4007C Dual Complementary Pair Plus Inverter
CD4007CM Dual Complementary Pair Plus Inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.