DM74ALS240A Datasheet | Fairchild Semiconductor

Description These octal 3-STATE bus drivers are designed to provide the designer with flexibility in implementing a bus interface with memory, microprocessor, or munication systems. The output 3-STATE gating control is organized into two separate groups of four buffers. The DM74ALS240A control inputs symmetrically enable the respective outputs when set logic LOW, while the DM74ALS241A has plementary enable gating. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown. This eliminates bus glitching problems that arise during power-up and power-down. Features s Advanced low power Schottky TTL process oxide-isolated ion-implanted s Functional and pin patible with the DM74LS counterpart s Improved switching performance with less power dissipation pared with the DM74LS counterpart s Switching response specified into 500Ω and 50 p F load s Switching response specifications guaranteed over full temperature and VCC supply range s PNP input design reduces input loading s Low level drive current: 74ALS = 24 m A Ordering Code: Order Number DM74ALS240AWM DM74ALS240ASJ DM74ALS240AN DM74ALS241AWM DM74ALS241AN Package Number M20B M20D N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74ALS240A DM74ALS241A © 2000 Fairchild Semiconductor Corporation DS006210 .fairchildsemi. - DM74ALS241A Function Tables DM74ALS240A Input G L L H A L H X Output Y H L Z 1G L L H Input 1A L H X DM74ALS241A Output Y L H Z 2G H H L Input...