DM9602 Datasheet | Fairchild Semiconductor

Description These dual resettable, retriggerable one shots have two inputs per function; one which is active HIGH, and one which is active LOW. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. When input conditions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. The retriggerable feature permits output pulse widths to be extended. In fact a continuous true output can be maintained by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at any time by applying a LOW logic level to the RESET pin. Retriggering may be inhibited by either connecting the Q output to an active HIGH input, or the Q output to an active LOW input. Features s 70 ns to ∞ output width range s Resettable and retriggerable- 0% to 100% duty cycle s TTL input gating- leading or trailing edge triggering s plementary TTL outputs s Optional retrigger lock-out capability s Pulse width pensated for VCC and temperature variations Ordering Code: Order Number DM9602N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Logic Diagrams Function Table Pin Numbers A H→L H X H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care B L L→H X CLR H H L Operation Trigger Trigger Reset © 2000 Fairchild Semiconductor Corporation DS006611 .fairchildsemi. Operating Rules 1. An external resistor (RX) and external capacitor (CX) are required as shown in the Logic Diagram. 2. The value of CX may vary from 0 to any necessary value available. If, however, the capacitor has leakages approaching 3.0 µA or if stray capacitance from either terminal to ground is more than 50 p F, the timing equations may not represent the pulse width obtained. 3. The output pulse with (t) is defined as follows: 6. Under any operating...