FAN6550 Datasheet | Fairchild Semiconductor

Features - - - - - - - - - - - - Can source and sink up to 2A continous, 3A peak No heatsink required Integrated Power MOSFETs Generates termination voltages for DDR SDRAM VREF input available for external voltage divider Separate voltages for VCCQ and PVDD Buffered VREF output VOUT of ±3% or less at 2A Minimum external ponents 0°C to 70°C operating range Shutdown for standby or suspend mode operation Thermal Shutdown ≈ 130ºC Description The FAN6550 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6550 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the FAN6550 output voltage is 50% of the voltage applied to VCCQ. The FAN6550 can also be used to produce various user-defined voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 2A of current while regulating an output VTT voltage to within 3% or less. Transient output currents of ±3A can also be acmodated. The FAN6550 can also be used in conjunction with series termination resisitors to provide an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. Block Diagram VCCQ AVCC VREFOUT 9 VDD VDD SHDN PVDD1 PVDD2 VL1 (VOUT) 3 OSCILLATOR/ RAMP GENERATOR 200kΩ - + VREF BUFFER VREFIN 11 200kΩ AGND 13 + - - R + ERROR AMP RAMP PARATOR Q S Q 6 VL2 (VOUT) VFB 10 8 DGND 4 PGND1 5 PGND2 REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION Pin Configuration FAN6550 16-Pin SOIC (M16) VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14...