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FDC6303N - Dual N-Channel Digital FET

General Description

These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • 25 V, 0.68 A continuous, 2 A Peak. RDS(ON) = 0.6 Ω @ VGS = 2.7 V RDS(ON) = 0.45 Ω @ VGS= 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple NPN digital transistors (IMHxA series) with one DMOS FET. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 Mark: .303 4 3 5 2 6 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG ESD Parameter Drain-Sour.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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August 1997 FDC6303N Digital FET, Dual N-Channel General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this one N-Channel FET can replace several digital transistors with different bias resistors like the IMHxA series. Features 25 V, 0.68 A continuous, 2 A Peak. RDS(ON) = 0.6 Ω @ VGS = 2.7 V RDS(ON) = 0.45 Ω @ VGS= 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits.