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FDC6321C - Dual N & P Channel / Digital FET

General Description

These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.0V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple dual NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 Mark:.321 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D2 S1 D1 4 3 G2 5 2 SuperSOT TM -6 S2 G1 6 1 Absolute Maximum Ratings Symbol Parameter TA = 25oC unless other.

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Other Datasheets by Fairchild (now onsemi)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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April 1999 FDC6321C Dual N & P Channel , Digital FET General Description These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual digital FET can replace several digital transistors with different bias resistors. Features N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.