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FDG6304P - Dual P-Channel/ Digital FET

Datasheet Summary

Description

These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Features

  • -25 V, -0.41 A continuous, -1.5 A peak. RDS(ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 D1 G2 S2 .04 D2 1 or 4.
  • 6 or 3 2 or 5 5 or 2 SC70-6 S1 G1 3 or 6 4 or 1.
  • The pinouts are sy.

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Datasheet Details

Part number FDG6304P
Manufacturer Fairchild Semiconductor
File Size 227.14 KB
Description Dual P-Channel/ Digital FET
Datasheet download datasheet FDG6304P Datasheet
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July 1999 FDG6304P Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features -25 V, -0.41 A continuous, -1.5 A peak. RDS(ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package.
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