FDG6304P Datasheet | Fairchild Semiconductor

Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features -25 V, -0.41 A continuous, -1.5 A peak. RDS(ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6k V Human Body Model). pact industry standard SC70-6 surface mount package. SC70-6 SOT-23 Super SOTTM-6 Super SOTTM-8 SO-8 SOT-223 D1 G2 S2 .04 D2 1 or 4 - 6 or 3 2 or 5 5 or 2 SC70-6 S1 G1 3 or 6 4 or 1 - - The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted Units VDSS VGSS ID PD TJ,TSTG ESD Drain-Source Voltage Gate-Source Voltage Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation (Note 1) -25 -8 -0.41 -1.5 0.3 -55 to 150 6.0 W °C k V Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100 p F / 1500 Ω) Thermal Resistance, Junction-to-Ambient THERMAL CHARACTERISTICS...