FDPF55N06 Datasheet | Fairchild Semiconductor

Features - - - - - - 55A, 60V, RDS(on) = 0.022 Ω @VGS = 10 V Low gate charge ( typical 30 n C) Low Crss ( typical 60 p F) Fast switching 100% avalanche tested Improved dv/dt capability Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and mutation mode. These devices are well suited for high efficient switched mode power supplies, active power factor correction, electronic lamp ballast based on half bridge topology. G G DS TO-220 FDP Series GD S TO-220F FDPF Series Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FDP55N06 60 55 34.8 220 ± 25 (Note 2) (Note 1) (Note 1) (Note 3) FDPF55N06 55 - 34.8 - 220 - 480 55 11.4 4.5 Units V A A A V m J A m J V/ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8∀ from case for 5 seconds 114 0.9 -55 to +150 300 48 0.4 - Drain current limited by maximum junction temperature Thermal Characteristics Symbol RθJC RθJS RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Typ. Thermal Resistance, Junction-to-Ambient FDP55N06 1.1 0.5 62.5 FDPF55N06 2.58 -62.5 Units °C/W °C/W °C/W ©2005 Fairchild Semiconductor Corporation .fairchildsemi....