FIN1019 Datasheet | Fairchild Semiconductor

FIN1019 3.3V LVDS High Speed Differential Driver/Receiver April 2001 Revised September 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350m V and the receiver translates LVDS signals, with a typical differential input threshold of 100m V, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.5ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s 100m V receiver input sensitivity s Fail safe protection open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 14-Lead SOIC and TSSOP packages save space Ordering Code: Order Number FIN1019M FIN1019MTC Package Number M14A MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Function Table Inputs RIN+ L H X DIN L H X Open- Circuit or Z H = HIGH Logic Level Z = High Impedance Connection Diagram Outputs RE L L H L DE H H L H DOUT+ L H Z L ROUT L H Z H DOUT- H L Z H RIN- H L X Fail Safe Condition Pin Descriptions Pin Name DIN DOUT+ DOUT- DE RIN+ RIN- ROUT RE VCC GND NC Description LVTTL Data Input Non-inverting LVDS Output Inverting LVDS Output Driver Enable (LVTTL, Active HIGH) Non-Inverting LVDS Input Inverting LVDS Input LVTTL Receiver Output Receiver Enable (LVTTL, Active LOW) Power Supply...