FIN1019 Datasheet | onsemi

3.3 V LVDS High Speed Differential Driver/Receiver General Description This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350 m V and the receiver translates LVDS signals, with a typical differential input threshold of 100 m V, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer. Features - Greater than 400 Mbs Data Rate - 3.3 V Power Supply Operation - 0.5 ns Maximum Differential Pulse Skew - 2.5 ns Maximum Propagation Delay - Low Power Dissipation - Power- Off Protection - 100 m V Receiver Input Sensitivity - Fail Safe Protection Open- circuit, Shorted and Terminated Conditions - Meets or Exceeds the TIA/EIA- 644 LVDS Standard - Flow- through Pinout Simplifies PCB Layout - 14- Lead TSSOP Package Save Space - This Device is Pb- Free, Halide Free and is Ro HS pliant FUNCTION TABLE RIN+ L H X RIN- H L X ROUT Fail Safe Condition DIN L L DE H DOUT+ L DOUT- H Open- Circuit or Z H = HIGH Logic Level Z = High Impedance L = LOW Logic Level X = Don’t Care Fail Safe = Open, Shorted, Terminated DATA SHEET...