FIN1028 Datasheet | Fairchild Semiconductor

FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver March 2001 Revised June 2003 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 m V, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1028 can be paired with its panion driver, the FIN1027, or any other LVDS driver. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 8-Lead SOIC and 8-terminal MLP packages save space Ordering Code: Order Number FIN1028M (Note 1) FIN1028MPX (Preliminary) Package Number M08A MLP08C Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square [TAPE and REEL] Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Name ROUT1, ROUT2 RIN1+, RIN2+ RIN1- , RIN2- VCC GND Description LVTTL Data Outputs Non-inverting LVDS Inputs Inverting LVDS Inputs Power Supply Ground Connection Diagrams Pin Assignment for SOIC Function Table Input RIN+ L H RIN+ H L Outputs ROUT L H H (Top View) Terminal Assignments for MLP Fail Safe Condition H = HIGH Logic Level L = LOW Logic Level Fail Safe = Open, Shorted, Terminated (Top Through View) © 2003 Fairchild Semiconductor Corporation DS500503 .fairchildsemi....