FIN1028 - 3.3V LVDS 2-Bit High Speed Differential Receiver

This page provides the datasheet information for the FIN1028, a member of the FIN 3.3V LVDS 2-Bit High Speed Differential Receiver family.

Product Overview

Fairchild Semiconductor

Part number	FIN1028
Manufacturer	Fairchild Semiconductor
File Size	746.91 KB
Description	3.3V LVDS 2-Bit High Speed Differential Receiver
Datasheet	FIN1028 Datasheet
Additional preview pages of the FIN1028 datasheet.

This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology.

The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.

s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 8-Lead SOIC and 8-terminal MLP packages save space Ordering Code: Order Number FIN1028M (Note 1) FIN1028MPX (Preliminary) Package Number M08A MLP0.

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Published: Mar 30, 2005 |