GENERAL DESCRIPTION
These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. FEATURES
-0.9 A, -30 V. RDS(ON) = 0.5 Ω @ VGS = -4.5 V RDS(ON) = 0.3 Ω @ VGS = -10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D G S ABSOLUTE MAXIMUM RATINGS
Symbol VDSS VGSS ID Parameter Drain-Source Voltage T A = 25°C unless otherwise noted NDS352AP -30 ±20 (Note 1a) Units V V A Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed ±0.9 ±10 PD TJ,TSTG Maximum Power Dissipation (Note 1a) (Note 1b) 0.5 0.46 -55 to 150 W Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC The...
Fairchild Semiconductor
