SCANPSC110F Datasheet | Fairchild Semiconductor

Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or bined serially. Addressing is acplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be acplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. Features s True IEEE1149.1 hierarchical and multidrop addressable capability s The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses s 3 IEEE 1149.1-patible configurable local scan ports s Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three s 32-bit TCK counter s 16-bit LFSR Signature pactor s L4 s local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs Ordering Code: Order Number SCANPSC110FSC Package Number M28B Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names TCKB TMSB TDIB TDOB TRST S(0,5) OE Description Backplane Test Clock Input Backplane Test Mode Select Input Backplane Test Data Input Backplane Test Data Output Asynchronous Test Reset Input (Active LOW) Address Select Port Local Scan Port Output Enable (Active LOW) TCKL(1- 3) Local Port Test...