74F524 Datasheet | Fairchild Semiconductor

Description The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit parator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow twos plement as well as magnitude pare. Linking inputs are provided for expansion to longer words. Features s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus parator with “equal to”, “greater than” and “less than” outputs s Cascadable in groups of eight bits s Open-collector expansion parator outputs for AND-wired s Twos plement or magnitude pare Ordering Code: Order Number 74F524SC 74F524PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009546 .fairchildsemi. Unit Loading/Fan Out U.L. Pin Names S0 , S1 C/SI CP SE M I/O0- I/O7 Description HIGH/LOW Mode Select Inputs Status Priority or Serial Data Input Clock Pulse Input (Active Rising Edge) Status Enable Input (Active LOW) pare Mode Select Input Parallel Data Inputs or 3-STATE Parallel Data Outputs C/SO LT EQ GT Note 1: OC = Open Collector Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A...